1. Field of the Invention
This invention relates to semiconductor storage devices such as synchronous dynamic random-access memories.
This application is based on Patent Application No. Hei 10-368193 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
In the semiconductor storage devices such as synchronous dynamic random-access memories (i.e., synchronous DRAMs), memory cells each storing a single bit, which is a minimum unit of data, are arranged in a matrix form and are connected together using word lines and bit lines. Herein, the bit lines are arbitrarily selected after the word lines are activated based on address signals given from the external (i.e., external device or system), so that read/write operations of data are performed on the memory cells by way of the selected bit lines.
Next, an example of a configuration of the conventional semiconductor storage device will be described by giving attention to the bit line(s) being selected.
Now, a basic configuration of the semiconductor storage device will be described with reference to FIG. 2, details of which will be described later.
In FIG. 2, memory cells "MC" are arranged in a memory cell array, wherein word lines "WL" are laid in directions of rows, while bit lines "BL" are laid in directions of columns. So, each memory cell MC is connected between the corresponding word line and bit line. To avoid an event in which the memory cells respectively connected to adjoining bit lines are simultaneously selected, each of the word lines is connected only with the memory cells, which belong to an odd-numbered column or an even-numbered column in the memory cell array consisting of rows and columns.
In addition, a single sense amplifier "SA" (e.g., SA0) is provided for two adjoining bit lines "BL" (e.g., BL0 and BL1). Herein, the sense amplifier SA is of a latch type, which is configured mainly by a flip-flop circuit. The sense amplifier is activated at a predetermined timing to sense (or latch) and amplify a weak data signal, which is given from the memory cell MC on the bit line BL.
Each of the bit lines BL is connected to a data line DB (i.e., DBa, DBb) by way of a column selecting transistor T (i.e., T01 to T32). Herein, a pair of bit lines connected to a same sense amplifier are connected to two data lines by two column selecting transistors respectively. Each column selecting transistor is turned on by a column selecting signal YS (i.e., YS01-YS04) so that each bit line is connected to the corresponding data line.
The data lines are connected to a data amplifier 410. The data amplifier 410 amplifies the data signal of the memory cell MC which appears on the data line. In the example of FIG. 2, eight bit lines BL0 to BL7 are collectively connected to the data amplifier 410 as one unit, which is repeated in the memory cell array. So, 512 bit lines are provided in the memory cell array in total.
FIG. 11 shows an example of a decoder circuit, which is conventionally used to produce the aforementioned column selecting signals by decoding column address signals being input from the external. In FIG. 11, column pre-decoders 321A to 323A perform pre-decoding on column address signals YA0 to YA8, which are input thereto by way of an address buffer circuit (not shown). Herein, each pre-decoder is activated to operate by a buffering signal .phi..sub.0.
A column decoder 330A decodes output signals of the column pre-decoders 321A to 323A to produce column selecting signals YS01 to YS04, which are used to control conductions of the column selecting transistors. There are provided sixty-four column decoders in total. Each column decoder (330A) is configured to specify any one of the column selecting signals YS01 to YS04 in response to the output signals of the column pre-decoder 321A. So, only one of the sixty-four column decoders is activated in response to the output signals of the column pre-decoders 322A and 323A.
Namely, the decoder circuit of FIG. 11 outputs 256 column selecting signals in total. Herein, only one of the column selecting signals is activated in response to the column address signal given from the external. There are provided two sets of the decoder circuit shown in FIG. 11, which output 512 column selecting signals in total. Each set is selected by the address signal YA8. Then, one of the 512 column selecting signals is selected at last.
In the aforementioned semiconductor storage device, the column selecting signals "YS" (i.e., YS01-YS04) output from the column decoder 330A make transition in synchronization with the column address signals input to the column pre-decoders 321A to 323A. Herein, each column selecting signal selects a pair of bit lines by controlling conductions of the column selecting transistors.
In order to minimize time lags (or deviations) in timing between column address signals due to wiring load, the conventional semiconductor storage device is designed such that the address buffer circuits are arranged on a chip in a concentrated manner, so that lengths of wires laid between the address buffer circuits and column pre-decoders are adjusted to be substantially identical to each other. To cope with increasing capacities of memories, it is necessary to reduce wiring areas as minimally as possible. In order to do so, wires used for the column address signals of the address buffer circuits are formed as groups, which are arranged adjacent to each other.
If the wires used for the column address signals are arranged to be adjacent to each other, a coupling capacity (or coupling capacitor) is formed between the wires. So, crosstalk is caused to occur between the wires due to the coupling capacity. In addition, a time lag is caused to occur in timing between the column address signals being input to the column pre-decoders, so that a time lag is correspondingly caused to occur in timing between the column selecting signals being output from the column decoder. This may cause a multiple selection of bit lines in which multiple (pairs of) bit lines are simultaneously selected.
Next, a description will be given with respect to a mechanism in which a time lag is caused to occur in timing between the column address signals due to the coupling capacity being formed between the wires. Herein, the description will be given concretely with attention to two adjoining wires. Suppose that column address signals on the two adjoining wires make level transition in a same direction, in which both of the column address signal change in level from L level (or low level) to H level (or high level) or from H level to L level. In that case, an electric potential difference is retained substantially constant between terminals of the coupling capacity being formed between the wires. So, there is almost no probability in which the coupling capacity is charged or discharged due to level transition of the column address signals. Therefore, the coupling capacity does not become apparent, so the column address signals on the wires are transmitted at a high speed without being influenced by the coupling capacity.
In contrast, if the column address signals on the two adjoining wires make level transition in different directions respectively, or if only one of the column address signals makes level transition, the coupling capacity must be charged or discharged, so that the coupling capacity becomes apparent. In that case, the column address signals on the wires are influenced by the coupling capacity, so time lags are caused to occur in timing between the column address signals as shown in FIG. 12A. Due to such time lags between the column address signals, time lags as show in FIG. 12B are correspondingly caused to occur in timing between output signals (or column selecting signals) of the column pre-decoders, which make transition in synchronization with the column address signals.
In FIG. 12A, reference symbols YFD, YFU show waveforms, which are related to a "high-speed" column address signal whose propagation speed is the fastest within the column address signals (YA0-YA8). That is, YFD shows a rise-up waveform of the high-speed column address signal, while YFU shows a fall-down waveform of the high-speed column address signal. In addition, reference symbols YLU, YLD show waveforms, which are related to a "low-speed" column address signal whose propagation speed is the lowest within the column address signals. That is, YLU shows a rise-up waveform of the low-speed column address signal, while YLD shows a fall-down waveform of the low-speed column address signal. In FIG. 12B, reference symbols PFD, PFU, PLU and PLD show output waveforms of the column pre-decoders. That is, the waveforms PFD, PFU are output in response to the waveforms YFD, YFU respectively, while the waveforms PLU, PLD are output in response to the waveforms YLU, YLD respectively.
Suppose that signals output from the column pre-decoders make level transition along the waveforms PFU, PLD respectively. In that case, multiple column selecting signals are instantaneously (or simultaneously) activated, so the bit lines are subjected to multiple selection. In contrast, in the case where signals output from the column pre-decoders make level transition along the waveforms PFD, PLU respectively, there is no probability in which multiple column selecting signals are simultaneously activated, so the bit lines are not subjected to multiple selection.
In some case, the address buffer circuits must be subjected to distributed arrangement due to limitation in layout of the semiconductor storage device. In that case, wires of address signals should be distributed as well. So, lengths of wires from the address buffer circuits and column pre-decoders are not necessarily made identical to each other. Therefore, different loads are applied to the wires respectively.
Thus, even if the address buffer circuits input the address signals at same clock timings, time lags are caused to occur in timing between the column address signals being input to the column pre-decoders. As a result, time lags are correspondingly caused to occur in timing between column selecting signals being output from the column pre-decoders.
If the time lags occur in timing between the column selecting signals, the bit lines are subjected to multiple selection, which causes problems as follows:
A first problem is deterioration of a write recovery characteristic. That is, when the bit lines BL0, BL1 being originally selected are changed with the bit lines BL2, BL3, the column selecting signal YS01 being originally activated is inactivated while the column selecting signal YS02 is activated in FIG. 2.
In the aforementioned condition, if the column selecting signal YS01 makes level transition along the waveform PLD while the column selecting signal YS02 makes level transition along the waveform PFU shown in FIG. 12B, there is provided a duration in which both of the column selecting signals YS01, YS02 are made active at H level. In such a duration, a pair of the column selecting transistors T01, T02 and a pair of the column selecting transistors T11, T12 are simultaneously turned on to establish conduction states. In that case, a data signal output from the sense amplifier SA0 interferes with a data signal output from the sense amplifier SA1, so that data read operations are disturbed. Particularly, in a read operation which is performed in a cycle after a write operation of data, the aforementioned interference between the data signals becomes apparent. This deteriorates the write recovery characteristic.
A second problem is deterioration of operation margins of the data amplifier due to insufficient precharge of the data lines. Normally, precharging of the data lines (DB) is performed to erase a data signal of one memory cell being remained on the data lines when the bit lines (BL) are changed over so that a data signal of another memory cell is output onto the data lines.
At the precharging of the data lines, if the column selecting transistors (e.g., T01, T02) are placed in conduction states so that the corresponding bit lines are connected to the data lines, the sense amplifier (e.g., SA1) having a relatively large drive capability drives the data lines presently being subjected to precharging. For this reason, the precharging is insufficiently performed on the data lines, so the data amplifier is reduced in operation margins.
It may be possible to employ a countermeasure in which the sense amplifier(s) is inactivated during the precharging so that the data lines will not be driven. In such a countermeasure, however, the data lines are connected with loads of the bit lines, so it may take time to perform the precharging on the data lines.
A third problem is dispersion of data read times (or access times). In FIG. 2, the data amplifier 410 is activated at the predetermined timing so as to amplify the data signals appearing on the data lines (DB), which are then forwarded to the following circuitry. The timing to activate the data amplifier 410 is set such that the data amplifier 410 operates when the data signal on the data line is increased to have a prescribed amplitude.
However, if a time lag occurs in timing between the column address signals (YS) as described before, a time lag is correspondingly caused to occur in transmission time between data signals which appear on the data lines from the bit lines (BL). As a result, there is dispersion in amplitude between the data signals on the data lines. This causes dispersion in the data read times.